Field of the Invention
The present invention relates in general to reissuing instructions in a microprocessor, and more particularly to a system and method of reissue parking to avoid inefficiencies associated with re-reissuing instructions.
Description of the Related Art
Many modern microprocessors are superscalar in which they include multiple execution units and are capable of issuing multiple instructions to the execution units in a single clock cycle. Many modern microprocessors also perform out-of-order execution. That is, the microprocessor may execute instructions out of the order specified by the program that includes the instructions. Superscalar out-of-order execution microprocessors typically attempt to maintain a relatively large pool of outstanding instructions so that they can take advantage of a larger amount of instruction parallelism.
The microprocessor executes the instructions of an instruction set architecture, such as the x86 instruction set architecture or the like. In many such microprocessors, the instructions of the instruction set architecture, often referred to as macroinstructions, are first translated into microinstructions (or micro-operations or “μops”) that are issued to a reservation stations module that dispatches the instructions to the execution units. The microinstructions are more generally referred to herein simply as the instructions. The instructions are also issued to a reorder buffer which ensures in-order retirement of the instructions.
The reservation stations module includes one or more queues and if any queue is full, the reservation stations module is unable to receive any of the instructions being issued. In a re-issue configuration, the microprocessor reverted to a reissue mode in which the rejected instructions had to be reissued from the reorder buffer. If the reservation stations module was still full, then the instructions had to be re-reissued again. During the re-reissue process, the instructions repeatedly circulated in the reissue pipeline path until the reservation stations module was not full, at which time the instructions could finally be submitted to the reservation station module to be ultimately dispatched for execution.
The re-reissue process was disadvantageous for various reasons. The determination of whether the reservation stations module was full occurred at one stage in the pipeline, and if full, the reissued instructions had to traverse multiple pipeline stages before being re-reissued again to the reservation stations module. In this manner, the re-reissue process caused delay and reduced performance of the microprocessor.